mirror of https://github.com/YosysHQ/yosys.git
37 lines
686 B
Verilog
37 lines
686 B
Verilog
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`define CONSTANT_CHECK \
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if (WIDTH === 'bx) begin \
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$display("FAIL"); \
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$finish; \
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end
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module top;
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parameter WIDTH = 32;
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integer j;
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initial begin
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`CONSTANT_CHECK
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if (WIDTH == 32) begin : procedural_conditional_block
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`CONSTANT_CHECK
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end
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case (WIDTH)
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32: `CONSTANT_CHECK
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default: ;
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endcase
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for (j = 0; j < 2; j = j + 1) begin : procedural_loop_block
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`CONSTANT_CHECK
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end
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end
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generate
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if (WIDTH == 32) begin : conditional_block
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initial `CONSTANT_CHECK
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end
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case (WIDTH)
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32: initial `CONSTANT_CHECK
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default: ;
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endcase
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genvar i;
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for (i = 0; i < 2; i = i + 1) begin : loop_block
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initial `CONSTANT_CHECK
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end
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endgenerate
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endmodule
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