mirror of https://github.com/YosysHQ/yosys.git
22 lines
296 B
Verilog
22 lines
296 B
Verilog
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// expect-wr-ports 1
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// expect-rd-ports 1
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// expect-rd-clk \clk
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module top(input clk, we, rae, input [7:0] addr, wd, output [7:0] rd);
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reg [7:0] mem[0:255];
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reg [7:0] rra;
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always @(posedge clk) begin
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if (we)
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mem[addr] <= wd;
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if (rae)
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rra <= addr;
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end
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assign rd = mem[rra];
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endmodule
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