yosys/tests/arch/efinix/lutram.ys

read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r
synth_efinix
cd lutram_1w1r
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_RAM_5K
select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D
Rename memory tests to lutram, add more xilinx tests 2019-12-12 19:44:37 -06:00			`read_verilog ../common/lutram.v`
			`hierarchy -top lutram_1w1r`
efinix: Use `memory_libmap` pass. 2022-03-05 19:21:53 -06:00			`synth_efinix`
Rename memory tests to lutram, add more xilinx tests 2019-12-12 19:44:37 -06:00			`cd lutram_1w1r`
Add new tests for Efinix architecture. Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail. 2019-09-23 07:51:41 -05:00			`select -assert-count 1 t:EFX_GBUFCE`
			`select -assert-count 1 t:EFX_RAM_5K`
			`select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D`