yosys/tests/asicworld/code_verilog_tutorial_mux_21.v

10 lines
150 B
Coq
Raw Normal View History

2013-01-05 04:13:26 -06:00
module mux_21 (a,b,sel,y);
input a, b;
output y;
input sel;
wire y;
assign y = (sel) ? b : a;
endmodule