mirror of https://github.com/YosysHQ/yosys.git
178 lines
3.1 KiB
Verilog
178 lines
3.1 KiB
Verilog
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// LUT RAMs for Virtex, Virtex 2, Spartan 3, Virtex 4.
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// The corresponding definition file is lutrams_xcv.txt
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module $__XILINX_LUTRAM_SP_ (...);
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parameter INIT = 0;
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parameter OPTION_ABITS = 4;
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output PORT_RW_RD_DATA;
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input PORT_RW_WR_DATA;
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input [OPTION_ABITS-1:0] PORT_RW_ADDR;
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input PORT_RW_WR_EN;
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input PORT_RW_CLK;
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generate
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case(OPTION_ABITS)
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4: RAM16X1S
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#(
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.INIT(INIT),
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)
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_TECHMAP_REPLACE_
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(
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.A0(PORT_RW_ADDR[0]),
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.A1(PORT_RW_ADDR[1]),
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.A2(PORT_RW_ADDR[2]),
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.A3(PORT_RW_ADDR[3]),
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.D(PORT_RW_WR_DATA),
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.O(PORT_RW_RD_DATA),
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.WE(PORT_RW_WR_EN),
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.WCLK(PORT_RW_CLK),
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);
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5: RAM32X1S
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#(
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.INIT(INIT),
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)
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_TECHMAP_REPLACE_
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(
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.A0(PORT_RW_ADDR[0]),
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.A1(PORT_RW_ADDR[1]),
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.A2(PORT_RW_ADDR[2]),
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.A3(PORT_RW_ADDR[3]),
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.A4(PORT_RW_ADDR[4]),
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.D(PORT_RW_WR_DATA),
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.O(PORT_RW_RD_DATA),
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.WE(PORT_RW_WR_EN),
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.WCLK(PORT_RW_CLK),
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);
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6: RAM64X1S
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#(
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.INIT(INIT),
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)
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_TECHMAP_REPLACE_
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(
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.A0(PORT_RW_ADDR[0]),
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.A1(PORT_RW_ADDR[1]),
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.A2(PORT_RW_ADDR[2]),
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.A3(PORT_RW_ADDR[3]),
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.A4(PORT_RW_ADDR[4]),
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.A5(PORT_RW_ADDR[5]),
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.D(PORT_RW_WR_DATA),
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.O(PORT_RW_RD_DATA),
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.WE(PORT_RW_WR_EN),
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.WCLK(PORT_RW_CLK),
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);
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7: RAM128X1S
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#(
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.INIT(INIT),
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)
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_TECHMAP_REPLACE_
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(
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.A0(PORT_RW_ADDR[0]),
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.A1(PORT_RW_ADDR[1]),
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.A2(PORT_RW_ADDR[2]),
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.A3(PORT_RW_ADDR[3]),
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.A4(PORT_RW_ADDR[4]),
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.A5(PORT_RW_ADDR[5]),
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.A6(PORT_RW_ADDR[6]),
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.D(PORT_RW_WR_DATA),
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.O(PORT_RW_RD_DATA),
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.WE(PORT_RW_WR_EN),
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.WCLK(PORT_RW_CLK),
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);
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default:
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$error("invalid OPTION_ABITS");
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endcase
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endgenerate
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endmodule
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module $__XILINX_LUTRAM_DP_ (...);
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parameter INIT = 0;
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parameter OPTION_ABITS = 4;
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output PORT_RW_RD_DATA;
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input PORT_RW_WR_DATA;
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input [OPTION_ABITS-1:0] PORT_RW_ADDR;
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input PORT_RW_WR_EN;
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input PORT_RW_CLK;
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output PORT_R_RD_DATA;
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input [OPTION_ABITS-1:0] PORT_R_ADDR;
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generate
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case (OPTION_ABITS)
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4: RAM16X1D
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#(
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.INIT(INIT),
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)
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_TECHMAP_REPLACE_
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(
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.A0(PORT_RW_ADDR[0]),
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.A1(PORT_RW_ADDR[1]),
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.A2(PORT_RW_ADDR[2]),
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.A3(PORT_RW_ADDR[3]),
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.D(PORT_RW_WR_DATA),
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.SPO(PORT_RW_RD_DATA),
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.WE(PORT_RW_WR_EN),
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.WCLK(PORT_RW_CLK),
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.DPRA0(PORT_R_ADDR[0]),
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.DPRA1(PORT_R_ADDR[1]),
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.DPRA2(PORT_R_ADDR[2]),
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.DPRA3(PORT_R_ADDR[3]),
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.DPO(PORT_R_RD_DATA),
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);
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5: RAM32X1D
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#(
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.INIT(INIT),
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)
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_TECHMAP_REPLACE_
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(
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.A0(PORT_RW_ADDR[0]),
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.A1(PORT_RW_ADDR[1]),
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.A2(PORT_RW_ADDR[2]),
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.A3(PORT_RW_ADDR[3]),
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.A4(PORT_RW_ADDR[4]),
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.D(PORT_RW_WR_DATA),
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.SPO(PORT_RW_RD_DATA),
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.WE(PORT_RW_WR_EN),
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.WCLK(PORT_RW_CLK),
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.DPRA0(PORT_R_ADDR[0]),
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.DPRA1(PORT_R_ADDR[1]),
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.DPRA2(PORT_R_ADDR[2]),
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.DPRA3(PORT_R_ADDR[3]),
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.DPRA4(PORT_R_ADDR[4]),
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.DPO(PORT_R_RD_DATA),
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);
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6: RAM64X1D
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#(
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.INIT(INIT),
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)
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_TECHMAP_REPLACE_
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(
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.A0(PORT_RW_ADDR[0]),
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.A1(PORT_RW_ADDR[1]),
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.A2(PORT_RW_ADDR[2]),
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.A3(PORT_RW_ADDR[3]),
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.A4(PORT_RW_ADDR[4]),
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.A5(PORT_RW_ADDR[5]),
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.D(PORT_RW_WR_DATA),
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.SPO(PORT_RW_RD_DATA),
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.WE(PORT_RW_WR_EN),
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.WCLK(PORT_RW_CLK),
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.DPRA0(PORT_R_ADDR[0]),
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.DPRA1(PORT_R_ADDR[1]),
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.DPRA2(PORT_R_ADDR[2]),
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.DPRA3(PORT_R_ADDR[3]),
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.DPRA4(PORT_R_ADDR[4]),
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.DPRA5(PORT_R_ADDR[5]),
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.DPO(PORT_R_RD_DATA),
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);
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default:
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$error("invalid OPTION_ABITS");
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endcase
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endgenerate
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endmodule
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