mirror of https://github.com/YosysHQ/yosys.git
17 lines
295 B
Plaintext
17 lines
295 B
Plaintext
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read_verilog <<EOT
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module sub(input i, output o, input j);
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foobar _TECHMAP_REPLACE_(i, o, j);
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wire _TECHMAP_REPLACE_.asdf = i ;
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endmodule
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EOT
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design -stash techmap
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read_verilog <<EOT
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module top(input i, output o);
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sub s0(i, o);
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endmodule
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EOT
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techmap -map %techmap
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select -assert-any w:s0.asdf
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