mirror of https://github.com/YosysHQ/yosys.git
88 lines
2.6 KiB
C++
88 lines
2.6 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/bitpattern.h"
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#include "kernel/log.h"
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#include <sstream>
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#include <stdlib.h>
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#include <stdio.h>
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#include <assert.h>
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#include <set>
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static void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)
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{
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BitPatternPool pool(sw->signal);
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for (size_t i = 0; i < sw->cases.size(); i++)
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{
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bool is_default = sw->cases[i]->compare.size() == 0 && !pool.empty();
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for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) {
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RTLIL::SigSpec sig = sw->cases[i]->compare[j];
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if (!sig.is_fully_const())
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continue;
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if (!pool.take(sig))
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sw->cases[i]->compare.erase(sw->cases[i]->compare.begin() + (j--));
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}
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if (!is_default) {
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if (sw->cases[i]->compare.size() == 0) {
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delete sw->cases[i];
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sw->cases.erase(sw->cases.begin() + (i--));
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counter++;
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continue;
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}
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if (pool.empty())
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sw->cases[i]->compare.clear();
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}
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for (auto switch_it : sw->cases[i]->switches)
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proc_rmdead(switch_it, counter);
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if (is_default)
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pool.take_all();
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}
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}
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struct ProcRmdeadPass : public Pass {
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ProcRmdeadPass() : Pass("proc_rmdead") { }
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n");
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extra_args(args, 1, design);
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int total_counter = 0;
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for (auto &mod_it : design->modules)
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for (auto &proc_it : mod_it.second->processes) {
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int counter = 0;
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for (auto switch_it : proc_it.second->root_case.switches)
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proc_rmdead(switch_it, counter);
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if (counter > 0)
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log("Removed %d dead cases from process %s in module %s.\n", counter,
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proc_it.first.c_str(), mod_it.first.c_str());
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total_counter += counter;
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}
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log("Removed a total of %d dead cases.\n", total_counter);
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}
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} ProcRmdeadPass;
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