mirror of https://github.com/YosysHQ/yosys.git
6 lines
104 B
Verilog
6 lines
104 B
Verilog
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module test (A, X, Y);
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input [7:0] A;
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output [7:0] X = A * 8'd 6;
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output [7:0] Y = A * 8'd 8;
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endmodule
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