mirror of https://github.com/YosysHQ/yosys.git
12 lines
235 B
Verilog
12 lines
235 B
Verilog
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module main(input clk);
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reg [3:0] counter = 0;
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always @(posedge clk) begin
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if (counter == 10)
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counter <= 0;
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else
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counter <= counter + 1;
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end
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assert property (counter != 15);
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// assert property (counter <= 10);
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endmodule
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