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33ca6994b7
yosys
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tests
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verilog
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.gitignore
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Setup tests/verilog properly
2020-05-11 12:30:20 -05:00
/*.log
/*.out
/run-test.mk
Update .gitignore Signed-off-by: David Shah <dave@ds0.me>
2020-10-01 09:53:14 -05:00
/const_arst.v
/const_sr.v
fixup verilog doubleslash test - add generated doubleslash.v to .gitignore - ensure backend verilog can be read again
2021-12-30 01:06:23 -06:00
/doubleslash.v