mirror of https://github.com/YosysHQ/yosys.git
8 lines
151 B
Coq
8 lines
151 B
Coq
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module TECH_AND18(input [17:0] in, output out);
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assign out = ∈
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endmodule
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module TECH_AND4(input [3:0] in, output out);
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assign out = ∈
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endmodule
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