mirror of https://github.com/YosysHQ/yosys.git
14 lines
244 B
Coq
14 lines
244 B
Coq
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module test(in1, in2, out);
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input in1;
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input in2;
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output out;
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wire synth_net_0;
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wire synth_net_1;
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BUF synth_BUF_0(.in(synth_net_1), .out(out
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));
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DIV1 synth_DIV(.in1(in1), .in2(in2), .rem(synth_net_0), .out(synth_net_1
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));
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endmodule
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