mirror of https://github.com/YosysHQ/yosys.git
14 lines
157 B
Coq
14 lines
157 B
Coq
|
module FlipFlop(clock, cs, ns);
|
||
|
|
input clock;
|
||
|
|
input cs;
|
||
|
|
output reg ns;
|
||
|
|
reg temp;
|
||
|
|
|
||
|
|
always @(posedge clock)
|
||
|
|
begin
|
||
|
|
temp <= cs;
|
||
|
|
ns <= temp;
|
||
|
|
end
|
||
|
|
|
||
|
|
endmodule
|