yosys/tests/hana/test_intermout_always_ff_4_...

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2013-01-05 04:13:26 -06:00
module FlipFlop(clk, cs, ns);
input clk;
input [31:0] cs;
output [31:0] ns;
integer is;
always @(posedge clk)
is <= cs;
assign ns = is;
endmodule