yosys/tests/hana/test_intermout_always_comb_...

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2013-01-05 04:13:26 -06:00
module test(a, b, c, d, z);
input a, b, c, d;
output z;
reg z, temp1, temp2;
always @(a or b or c or d)
begin
temp1 = a ^ b;
temp2 = c ^ d;
z = temp1 ^ temp2;
end
endmodule