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42 lines
1.3 KiB
Plaintext
42 lines
1.3 KiB
Plaintext
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read_verilog <<EOT
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module xilinx_srl_static_test(input i, clk, output [1:0] q);
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reg head = 1'b0;
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reg [3:0] shift1 = 4'b0000;
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reg [3:0] shift2 = 4'b0000;
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always @(posedge clk) begin
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head <= i;
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shift1 <= {shift1[2:0], head};
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shift2 <= {shift2[2:0], head};
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end
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assign q = {shift2[3], shift1[3]};
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endmodule
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EOT
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design -save read
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hierarchy -top xilinx_srl_static_test
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proc
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#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
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equiv_opt -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd xilinx_srl_static_test # Constrain all select calls below inside the top module
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stat
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select -assert-count 1 t:BUFG
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select -assert-count 1 t:SRL16E
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select -assert-none t:BUFG t:SRL16E %% t:* %D
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design -load read
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hierarchy -top xilinx_srl_static_test
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proc
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nosrl -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd xilinx_srl_static_test # Constrain all select calls below inside the top module
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stat
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select -assert-count 1 t:BUFG
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select -assert-count 5 t:FDRE
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select -assert-none t:BUFG t:FDRE %% t:* %D
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