mirror of https://github.com/YosysHQ/yosys.git
93 lines
3.2 KiB
C++
93 lines
3.2 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include <sstream>
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#include <set>
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#include <stdlib.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct MemoryMemxPass : public Pass {
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MemoryMemxPass() : Pass("memory_memx", "emulate vlog sim behavior for mem ports") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_memx [selection]\n");
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log("\n");
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log("This pass adds additional circuitry that emulates the Verilog simulation\n");
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log("behavior for out-of-bounds memory reads and writes.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
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log_header(design, "Executing MEMORY_MEMX pass (converting $mem cells to logic and flip-flops).\n");
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extra_args(args, 1, design);
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for (auto module : design->selected_modules())
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{
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vector<Cell*> mem_port_cells;
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for (auto cell : module->selected_cells())
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if (cell->type.in("$memrd", "$memwr"))
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mem_port_cells.push_back(cell);
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for (auto cell : mem_port_cells)
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{
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IdString memid = cell->getParam("\\MEMID").decode_string();
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RTLIL::Memory *mem = module->memories.at(memid);
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int lowest_addr = mem->start_offset;
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int highest_addr = mem->start_offset + mem->size - 1;
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SigSpec addr = cell->getPort("\\ADDR");
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addr.extend_u0(32);
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SigSpec addr_ok = module->Nex(NEW_ID, module->ReduceXor(NEW_ID, addr), module->ReduceXor(NEW_ID, {addr, State::S1}));
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if (lowest_addr != 0)
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addr_ok = module->LogicAnd(NEW_ID, addr_ok, module->Ge(NEW_ID, addr, lowest_addr));
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addr_ok = module->LogicAnd(NEW_ID, addr_ok, module->Le(NEW_ID, addr, highest_addr));
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if (cell->type == "$memrd")
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{
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if (cell->getParam("\\CLK_ENABLE").as_bool())
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log_error("Cell %s.%s (%s) has an enabled clock. Clocked $memrd cells are not supported by memory_memx!\n",
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log_id(module), log_id(cell), log_id(cell->type));
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SigSpec rdata = cell->getPort("\\DATA");
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Wire *raw_rdata = module->addWire(NEW_ID, GetSize(rdata));
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module->addMux(NEW_ID, SigSpec(State::Sx, GetSize(rdata)), raw_rdata, addr_ok, rdata);
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cell->setPort("\\DATA", raw_rdata);
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}
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if (cell->type == "$memwr")
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{
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SigSpec en = cell->getPort("\\EN");
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en = module->And(NEW_ID, en, addr_ok.repeat(GetSize(en)));
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cell->setPort("\\EN", en);
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}
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}
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}
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}
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} MemoryMemxPass;
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PRIVATE_NAMESPACE_END
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