mirror of https://github.com/YosysHQ/yosys.git
34 lines
920 B
Verilog
34 lines
920 B
Verilog
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module RAM_WREN (
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input PORT_A_CLK,
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input [ABITS-1:0] PORT_A_ADDR,
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input [WIDTH-1:0] PORT_A_WR_DATA,
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output reg [WIDTH-1:0] PORT_A_RD_DATA,
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input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN,
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input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE
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);
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parameter ABITS=4;
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parameter WIDTH=8;
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parameter PORT_A_WR_EN_WIDTH=1;
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parameter PORT_A_WR_BE_WIDTH=0;
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parameter OPTION_BYTESIZE=WIDTH;
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parameter WB=OPTION_BYTESIZE;
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reg [WIDTH-1:0] mem [0:2**ABITS-1];
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integer i;
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always @(posedge PORT_A_CLK) begin
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for (i=0; i<PORT_A_WR_EN_WIDTH; i=i+1) // use PORT_A_WR_EN
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if (!PORT_A_WR_BE_WIDTH && PORT_A_WR_EN[i])
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mem[PORT_A_ADDR][i*WB+:WB] <= PORT_A_WR_DATA[i*WB+:WB];
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for (i=0; i<PORT_A_WR_BE_WIDTH; i=i+1) // use PORT_A_WR_BE
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if (PORT_A_WR_EN[0] && PORT_A_WR_BE[i])
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mem[PORT_A_ADDR][i*WB+:WB] <= PORT_A_WR_DATA[i*WB+:WB];
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end
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always @(posedge PORT_A_CLK)
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if (!PORT_A_WR_EN[0])
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PORT_A_RD_DATA <= mem[PORT_A_ADDR];
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endmodule
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