mirror of https://github.com/YosysHQ/yosys.git
22 lines
473 B
Verilog
22 lines
473 B
Verilog
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module parallel_if();
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reg [3:0] counter;
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wire clk,reset,enable, up_en, down_en;
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always @ (posedge clk)
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// If reset is asserted
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if (reset == 1'b0) begin
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counter <= 4'b0000;
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end else begin
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// If counter is enable and up count is mode
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if (enable == 1'b1 && up_en == 1'b1) begin
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counter <= counter + 1'b1;
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end
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// If counter is enable and down count is mode
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if (enable == 1'b1 && down_en == 1'b1) begin
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counter <= counter - 1'b1;
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end
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end
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endmodule
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