mirror of https://github.com/YosysHQ/yosys.git
19 lines
495 B
Verilog
19 lines
495 B
Verilog
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//-----------------------------------------------------
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// Design Name : full_adder_gates
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// File Name : full_adder_gates.v
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// Function : Full Adder Using Gates
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module full_adder_gates(x,y,z,sum,carry);
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input x,y,z;
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output sum,carry;
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wire and1,and2,and3,sum1;
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and U_and1 (and1,x,y),
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U_and2 (and2,x,z),
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U_and3 (and3,y,z);
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or U_or (carry,and1,and2,and3);
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xor U_sum (sum,x,y,z);
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endmodule
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