mirror of https://github.com/YosysHQ/yosys.git
33 lines
545 B
Plaintext
33 lines
545 B
Plaintext
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read_ilang << EOF
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module \top
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wire input 1 \A
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wire input 2 \B
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wire input 3 \C
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wire input 4 \D
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wire output 5 \Z
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cell \LUT4 $0
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parameter \INIT 16'1111110011000000
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connect \A \A
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connect \B \B
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connect \C \C
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connect \D \D
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connect \Z \Z
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end
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end
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EOF
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read_verilog -lib +/ecp5/cells_sim.v
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equiv_opt -assert -map +/ecp5/cells_sim.v opt_lut_ins -tech ecp5
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design -load postopt
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select -assert-count 1 top/t:LUT4
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select -assert-count 0 top/w:A %co top/t:LUT4 %i
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select -assert-count 1 top/w:B %co top/t:LUT4 %i
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