mirror of https://github.com/YosysHQ/yosys.git
23 lines
305 B
Coq
23 lines
305 B
Coq
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module misc1 (a,b,c,d,y);
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input a, b,c,d;
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output y;
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wire net1,net2,net3;
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supply1 vdd;
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supply0 vss;
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// y = !((a+b+c).d)
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pmos p1 (vdd,net1,a);
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pmos p2 (net1,net2,b);
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pmos p3 (net2,y,c);
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pmos p4 (vdd,y,d);
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nmos n1 (vss,net3,a);
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nmos n2 (vss,net3,b);
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nmos n3 (vss,net3,c);
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nmos n4 (net3,y,d);
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endmodule
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