mirror of https://github.com/YosysHQ/yosys.git
118 lines
2.7 KiB
Verilog
118 lines
2.7 KiB
Verilog
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module constgtge(C, A, B, Y);
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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output Y;
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input C;
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wire [A_WIDTH:0] ch;
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genvar n;
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generate
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if (B_WIDTH > A_WIDTH) begin
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// Fail
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end else begin
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assign ch[0] = C;
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for (n = 0; n < A_WIDTH; n = n + 1) begin
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if (n < B_WIDTH) begin
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assign ch[n + 1] = B[n] ? (ch[n] && A[n]) : (ch[n] || A[n]);
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end else begin
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assign ch[n + 1] = ch[n] || A[n];
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end
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end
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assign Y = ch[A_WIDTH];
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end
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endgenerate
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endmodule
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module constltle(C, A, B, Y);
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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output Y;
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input C;
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wire [A_WIDTH:0] ch;
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genvar n;
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generate
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if (B_WIDTH > A_WIDTH) begin
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// Fail
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end else begin
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assign ch[0] = C;
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for (n = 0; n < A_WIDTH; n = n + 1) begin
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if (n < B_WIDTH) begin
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assign ch[n + 1] = !B[n] ? (ch[n] && !A[n]) : (ch[n] || !A[n]);
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end else begin
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assign ch[n + 1] = ch[n] && !A[n];
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end
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end
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assign Y = ch[A_WIDTH];
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end
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endgenerate
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endmodule
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(* techmap_celltype = "$ge $gt $le $lt" *)
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module _map_const_cmp_(A, B, Y);
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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parameter Y_WIDTH = 0;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] Y;
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parameter _TECHMAP_CELLTYPE_ = "";
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parameter _TECHMAP_CONSTMSK_A_ = 0;
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parameter _TECHMAP_CONSTVAL_A_ = 0;
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parameter _TECHMAP_CONSTMSK_B_ = 0;
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parameter _TECHMAP_CONSTVAL_B_ = 0;
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wire [1023:0] _TECHMAP_DO_ = "opt -fast;";
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wire [A_WIDTH:0] ch;
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genvar n;
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generate
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if (Y_WIDTH != 1 || A_SIGNED || B_SIGNED)
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wire _TECHMAP_FAIL_ = 1;
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else if (&_TECHMAP_CONSTMSK_A_) begin
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if (A_WIDTH > B_WIDTH)
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wire _TECHMAP_FAIL_ = 1;
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else if (_TECHMAP_CELLTYPE_ == "$lt" || _TECHMAP_CELLTYPE_ == "$le")
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constgtge #(.A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH))
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_TECHMAP_REPLACE_(.A(B), .B(A), .Y(Y),
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.C(_TECHMAP_CELLTYPE_ == "$lt"));
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else
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constltle #(.A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH))
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_TECHMAP_REPLACE_(.A(B), .B(A), .Y(Y),
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.C(_TECHMAP_CELLTYPE_ == "$gt"));
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end else if (&_TECHMAP_CONSTMSK_B_) begin
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if (B_WIDTH > A_WIDTH)
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wire _TECHMAP_FAIL_ = 1;
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else if (_TECHMAP_CELLTYPE_ == "$lt" || _TECHMAP_CELLTYPE_ == "$le")
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constltle #(.A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH))
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_TECHMAP_REPLACE_(.A(A), .B(B), .Y(Y),
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.C(_TECHMAP_CELLTYPE_ == "$le"));
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else
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constgtge #(.A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH))
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_TECHMAP_REPLACE_(.A(A), .B(B), .Y(Y),
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.C(_TECHMAP_CELLTYPE_ == "$ge"));
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end else
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wire _TECHMAP_FAIL_ = 1;
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endgenerate
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endmodule
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