mirror of https://github.com/YosysHQ/yosys.git
60 lines
1.5 KiB
Verilog
60 lines
1.5 KiB
Verilog
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// Note: case_expr_{,non_}const.v should be modified in tandem to ensure both
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// the constant and non-constant case evaluation logic is covered
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module top(
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// expected to output all 1s
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output reg a, b, c, d, e, f, g, h
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);
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reg x_1b0 = 1'b0;
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reg x_1b1 = 1'b1;
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reg signed x_1sb0 = 1'sb0;
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reg signed x_1sb1 = 1'sb1;
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reg [1:0] x_2b0 = 2'b0;
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reg [1:0] x_2b11 = 2'b11;
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reg signed [1:0] x_2sb01 = 2'sb01;
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reg signed [1:0] x_2sb11 = 2'sb11;
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reg [2:0] x_3b0 = 3'b0;
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initial begin
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case (x_2b0)
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x_1b0: a = 1;
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default: a = 0;
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endcase
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case (x_2sb11)
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x_2sb01: b = 0;
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x_1sb1: b = 1;
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endcase
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case (x_2sb11)
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x_1sb0: c = 0;
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x_1sb1: c = 1;
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endcase
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case (x_2sb11)
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x_1b0: d = 0;
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x_1sb1: d = 0;
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default: d = 1;
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endcase
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case (x_2b11)
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x_1sb0: e = 0;
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x_1sb1: e = 0;
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default: e = 1;
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endcase
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case (x_1sb1)
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x_1sb0: f = 0;
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x_2sb11: f = 1;
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default: f = 0;
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endcase
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case (x_1sb1)
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x_1sb0: g = 0;
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x_3b0: g = 0;
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x_2sb11: g = 0;
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default: g = 1;
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endcase
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case (x_1sb1)
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x_1sb0: h = 0;
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x_1b1: h = 1;
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x_3b0: h = 0;
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x_2sb11: h = 0;
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default: h = 0;
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endcase
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end
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endmodule
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