yosys/docs/source/yosys_internals/flow/index.rst

Internal flow
=============


A (usually short) synthesis script controls Yosys.

This scripts contain three types of commands:

- **Frontends**, that read input files (usually Verilog);
- **Passes**, that perform transformations on the design in memory;
- **Backends**, that write the design in memory to a file (various formats are
  available: Verilog, BLIF, EDIF, SPICE, BTOR, . . .).

.. toctree:: 
	:maxdepth: 2

	overview
	control_and_data
	verilog_frontend
Reorganising documentation Also changing to furo theme. 2023-08-02 16:20:29 -05:00			`Internal flow`
			`=============`

Move presentation intro example Rework images makefile a bit to get it to import and build from resources folder(s). Currently requires running twice from a clean build due to the way it finds `.dot` files to convert. 2023-08-02 16:20:29 -05:00
			`A (usually short) synthesis script controls Yosys.`

			`This scripts contain three types of commands:`

			`- Frontends, that read input files (usually Verilog);`
			`- Passes, that perform transformations on the design in memory;`
			`- Backends, that write the design in memory to a file (various formats are`
			`available: Verilog, BLIF, EDIF, SPICE, BTOR, . . .).`

Reorganising documentation Also changing to furo theme. 2023-08-02 16:20:29 -05:00			`.. toctree::`
			`:maxdepth: 2`

			`overview`
			`control_and_data`
			`verilog_frontend`