mirror of https://github.com/YosysHQ/yosys.git
60 lines
1.9 KiB
Verilog
60 lines
1.9 KiB
Verilog
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module VCC (output V);
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assign V = 1'b1;
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endmodule // VCC
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module GND (output G);
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assign G = 1'b0;
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endmodule // GND
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/* Altera Arria 10 GX devices Input Buffer Primitive */
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module twentynm_io_ibuf (output o, input i, input ibar);
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assign ibar = ibar;
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assign o = i;
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endmodule // twentynm_io_ibuf
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/* Altera Arria 10 GX devices Output Buffer Primitive */
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module twentynm_io_obuf (output o, input i, input oe);
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assign o = i;
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assign oe = oe;
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endmodule // twentynm_io_obuf
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/* Altera Arria 10 GX LUT Primitive */
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module twentynm_lcell_comb (output combout, cout, sumout,
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input dataa, datab, datac, datad,
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input datae, dataf, datag, cin,
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input sharein);
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parameter lut_mask = 64'hFFFFFFFFFFFFFFFF;
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parameter dont_touch = "off";
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parameter lpm_type = "twentynm_lcell_comb";
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parameter shared_arith = "off";
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parameter extended_lut = "off";
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// TODO: This is still WIP
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initial begin
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$display("Simulation model is still under investigation\n");
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end
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endmodule // twentynm_lcell_comb
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