mirror of https://github.com/YosysHQ/yosys.git
36 lines
598 B
Plaintext
36 lines
598 B
Plaintext
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logger -expect-no-warnings
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read_verilog -formal <<EOT
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module top(input clk);
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reg signed [3:0] value = -1;
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reg ready = 0;
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always @(posedge clk) begin
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if (ready)
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assert ($past(value) == -1);
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ready <= 1;
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end
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endmodule
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EOT
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prep -top top
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sim -n 3 -clock clk
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design -reset
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read_verilog -formal <<EOT
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module top(input clk);
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reg signed [3:0] value = -1;
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reg ready = 0;
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always @(posedge clk) begin
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if (ready)
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assert ($past(value + 4'b0000) == 15);
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ready <= 1;
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end
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endmodule
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EOT
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prep -top top
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sim -n 3 -clock clk
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