mirror of https://github.com/YosysHQ/yosys.git
16 lines
238 B
Plaintext
16 lines
238 B
Plaintext
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read_verilog -sv <<EOF
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module top;
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integer x, y;
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initial y = (x += 1);
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endmodule
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EOF
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design -reset
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logger -expect error "syntax error, unexpected TOK_ID" 1
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read_verilog <<EOF
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module top;
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integer x, y;
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initial y = (x += 1);
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endmodule
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EOF
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