mirror of https://github.com/YosysHQ/yosys.git
49 lines
1.2 KiB
Verilog
49 lines
1.2 KiB
Verilog
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module \$reduce_or (A, Y);
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parameter A_SIGNED = 0;
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parameter A_WIDTH = 0;
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parameter Y_WIDTH = 0;
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input [A_WIDTH-1:0] A;
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output [Y_WIDTH-1:0] Y;
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function integer min;
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input integer a, b;
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begin
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if (a < b)
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min = a;
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else
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min = b;
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end
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endfunction
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genvar i;
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generate begin
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if (A_WIDTH == 0) begin
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assign Y = 0;
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end
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if (A_WIDTH == 1) begin
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assign Y = A;
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end
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if (A_WIDTH == 2) begin
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wire ybuf;
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OR3X1 g (.A(A[0]), .B(A[1]), .C(1'b0), .Y(ybuf));
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assign Y = ybuf;
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end
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if (A_WIDTH == 3) begin
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wire ybuf;
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OR3X1 g (.A(A[0]), .B(A[1]), .C(A[2]), .Y(ybuf));
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assign Y = ybuf;
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end
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if (A_WIDTH > 3) begin
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localparam next_stage_sz = (A_WIDTH+2) / 3;
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wire [next_stage_sz-1:0] next_stage;
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for (i = 0; i < next_stage_sz; i = i+1) begin
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localparam bits = min(A_WIDTH - 3*i, 3);
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assign next_stage[i] = |A[3*i +: bits];
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end
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assign Y = |next_stage;
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end
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end endgenerate
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endmodule
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