mirror of https://github.com/YosysHQ/yosys.git
18 lines
326 B
Plaintext
18 lines
326 B
Plaintext
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# pitfall
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read_verilog cmos.v
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prep -top cmos_demo
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techmap
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abc -liberty ../intro/mycells.lib;;
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show -format dot -prefix cmos_00
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# reset
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design -reset
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# fixed output
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read_verilog cmos.v
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prep -top cmos_demo
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techmap
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splitnets -ports
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abc -liberty ../intro/mycells.lib;;
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show -lib ../intro/mycells.v -format dot -prefix cmos_01
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