mirror of https://github.com/YosysHQ/yosys.git
29 lines
397 B
Systemverilog
29 lines
397 B
Systemverilog
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module top(
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input wire [31:0] i,
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output wire [31:0] x, y, z
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);
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`define BAR(a) a
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`define FOO(a = function automatic [31:0] f) a
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`BAR(function automatic [31:0] a);
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input [31:0] i;
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a = i * 2;
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endfunction
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`FOO();
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input [31:0] i;
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f = i * 3;
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endfunction
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`FOO(function automatic [31:0] b);
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input [31:0] i;
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b = i * 5;
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endfunction
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assign x = a(i);
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assign y = f(i);
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assign z = b(i);
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endmodule
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