mirror of https://github.com/YosysHQ/yosys.git
5 lines
180 B
Verilog
5 lines
180 B
Verilog
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// Any inverters not folded into LUTs are mapped to a LUT of their own
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module \$__CC_NOT (input A, output Y);
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CC_LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(A), .O(Y));
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endmodule
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