mirror of https://github.com/YosysHQ/yosys.git
5 lines
105 B
Verilog
5 lines
105 B
Verilog
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module primetest(p, a, b, ok);
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input [15:0] p, a, b;
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output ok = p != a*b || a == 1 || b == 1;
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endmodule
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