mirror of https://github.com/YosysHQ/yosys.git
7 lines
152 B
Plaintext
7 lines
152 B
Plaintext
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read_verilog -sv -mem2reg mem_bounds.sv
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proc
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flatten
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opt -full
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select -module top
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sat -verify -seq 1 -tempinduct -prove-asserts -show-all -enable_undef
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