yosys/tests/asicworld/code_verilog_tutorial_task_...

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2013-01-05 04:13:26 -06:00
module task_global();
reg [7:0] temp_out;
reg [7:0] temp_in;
task convert;
begin
temp_out = (9/5) *( temp_in + 32);
end
endtask
endmodule