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12 lines
173 B
Systemverilog
12 lines
173 B
Systemverilog
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module top(
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output logic [5:0] out
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);
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always_comb begin
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out = '0;
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case (1'b1 << 1)
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2'b10: out = '1;
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default: out = '0;
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endcase
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end
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endmodule
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