yosys/passes/tests/flowmap/pack1p.v

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2019-01-04 07:06:51 -06:00
// Like pack1.v, but results in a simpler network.
module top(...);
input a,b,c,d,e,f,g,h;
wire x = c|d;
wire y = e&f;
wire u = a&b;
wire v = x|y;
wire w = g&h;
output s = u|v;
output t = v|w;
endmodule