yosys/tests/hana/test_intermout_always_latch...

10 lines
131 B
Coq
Raw Normal View History

2013-01-05 04:13:26 -06:00
module test(en, in, out);
input en;
input [1:0] in;
output reg [2:0] out;
always @ (en or in)
if(en)
out = in + 1;
endmodule