mirror of https://github.com/YosysHQ/yosys.git
40 lines
1.3 KiB
ReStructuredText
40 lines
1.3 KiB
ReStructuredText
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The :cmd:ref:`abc` command
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. todo:: discuss abc (more stable) vs abc9 (newer, possibly better)
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The :cmd:ref:`abc` command provides an interface to ABC_, an open source tool
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for low-level logic synthesis.
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.. _ABC: http://www.eecs.berkeley.edu/~alanmi/abc/
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The :cmd:ref:`abc` command processes a netlist of internal gate types and can
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perform:
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- logic minimization (optimization)
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- mapping of logic to standard cell library (liberty format)
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- mapping of logic to k-LUTs (for FPGA synthesis)
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Optionally :cmd:ref:`abc` can process registers from one clock domain and
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perform sequential optimization (such as register balancing).
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ABC is also controlled using scripts. An ABC script can be specified to use more
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advanced ABC features. It is also possible to write the design with
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:cmd:ref:`write_blif` and load the output file into ABC outside of Yosys.
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Example
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^^^^^^^
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.. todo:: describe ``abc`` images
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.. literalinclude:: /code_examples/synth_flow/abc_01.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/abc_01.v``
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.. literalinclude:: /code_examples/synth_flow/abc_01.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/abc_01.ys``
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.. figure:: /_images/code_examples/synth_flow/abc_01.*
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:class: width-helper
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