mirror of https://github.com/YosysHQ/yosys.git
48 lines
895 B
Verilog
48 lines
895 B
Verilog
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module \$__XILINX_URAM288 (CLK2, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CLKPOL2 = 1;
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input CLK2;
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input [11:0] A1ADDR;
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output [71:0] A1DATA;
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input A1EN;
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input [11:0] B1ADDR;
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input [71:0] B1DATA;
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input [8:0] B1EN;
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URAM288 #(
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.BWE_MODE_A("PARITY_INDEPENDENT"),
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.BWE_MODE_B("PARITY_INDEPENDENT"),
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.EN_AUTO_SLEEP_MODE("FALSE"),
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.IREG_PRE_A("FALSE"),
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.IREG_PRE_B("FALSE"),
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.IS_CLK_INVERTED(!CLKPOL2),
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.OREG_A("FALSE"),
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.OREG_B("FALSE")
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) _TECHMAP_REPLACE_ (
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.ADDR_A({11'b0, A1ADDR}),
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.BWE_A(9'b0),
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.DIN_A(72'b0),
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.EN_A(A1EN),
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.RDB_WR_A(1'b0),
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.INJECT_DBITERR_A(1'b0),
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.INJECT_SBITERR_A(1'b0),
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.RST_A(1'b0),
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.DOUT_A(A1DATA),
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.ADDR_B({11'b0, B1ADDR}),
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.BWE_B(B1EN),
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.DIN_B(B1DATA),
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.EN_B(|B1EN),
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.RDB_WR_B(1'b1),
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.INJECT_DBITERR_B(1'b0),
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.INJECT_SBITERR_B(1'b0),
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.RST_B(1'b0),
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.CLK(CLK2),
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.SLEEP(1'b0)
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);
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endmodule
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