mirror of https://github.com/YosysHQ/yosys.git
18 lines
781 B
Bash
18 lines
781 B
Bash
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#!/bin/bash
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set -ex
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if [ -z $ISE_DIR ]; then
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ISE_DIR=/opt/Xilinx/ISE/14.7
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fi
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sed 's/DSP48A1/MARKER1/; s/DSP48A/DSP48A_UUT/; s/MARKER1/DSP48A1_UUT/; /module DSP48A_UUT/,/endmodule/ p; /module DSP48A1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp48a1_model_uut.v
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if [ ! -f "test_dsp48a1_model_ref.v" ]; then
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cp $ISE_DIR/ISE_DS/ISE/verilog/src/unisims/DSP48A1.v test_dsp48a1_model_ref.v
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fi
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if [ ! -f "test_dsp48a_model_ref.v" ]; then
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cp $ISE_DIR/ISE_DS/ISE/verilog/src/unisims/DSP48A.v test_dsp48a_model_ref.v
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fi
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for tb in mult_allreg mult_noreg mult_inreg
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do
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iverilog -s $tb -s glbl -o test_dsp48a1_model test_dsp48a1_model.v test_dsp48a1_model_uut.v test_dsp48a1_model_ref.v test_dsp48a_model_ref.v $ISE_DIR/ISE_DS/ISE/verilog/src/glbl.v
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vvp -N ./test_dsp48a1_model
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done
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