mirror of https://github.com/YosysHQ/yosys.git
82 lines
2.7 KiB
C++
82 lines
2.7 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Pmux2ShiftxPass : public Pass {
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Pmux2ShiftxPass() : Pass("pmux2shiftx", "transform $pmux cells to $shiftx cells") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" pmux2shiftx [selection]\n");
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log("\n");
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log("This pass transforms $pmux cells to $shiftx cells.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing PMUX2SHIFTX pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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for (auto cell : module->selected_cells())
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{
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if (cell->type != "$pmux")
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continue;
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// Create a new encoder, out of a $pmux, that takes
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// the existing pmux's 'S' input and transforms it
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// back into a binary value
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RTLIL::SigSpec shiftx_a;
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RTLIL::SigSpec pmux_s;
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int s_width = cell->getParam("\\S_WIDTH").as_int();
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if (!cell->getPort("\\A").is_fully_undef()) {
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++s_width;
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shiftx_a.append(cell->getPort("\\A"));
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pmux_s.append(module->Not(NEW_ID, module->ReduceOr(NEW_ID, cell->getPort("\\S"))));
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}
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const int clog2width = ceil(log2(s_width));
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RTLIL::SigSpec pmux_b;
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for (int i = s_width-1; i >= 0; i--)
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pmux_b.append(RTLIL::Const(i, clog2width));
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shiftx_a.append(cell->getPort("\\B"));
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pmux_s.append(cell->getPort("\\S"));
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RTLIL::SigSpec pmux_y = module->addWire(NEW_ID, clog2width);
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module->addPmux(NEW_ID, RTLIL::Const(RTLIL::Sx, clog2width), pmux_b, pmux_s, pmux_y);
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module->addShiftx(NEW_ID, shiftx_a, pmux_y, cell->getPort("\\Y"));
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module->remove(cell);
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}
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}
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} Pmux2ShiftxPass;
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PRIVATE_NAMESPACE_END
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