yosys/docs/source/code_examples/show/example_show.ys

mirror of https://github.com/YosysHQ/yosys.git
read_verilog example.v
show -pause # first
proc
show -pause # second
opt
show -pause # third
Docs: interactive investigation More `literalinclude` and references to source. Adding `example_show.ys` and `example_lscd.ys`. Rename `example_00` et al to `example_first` et al. Also some other minor tidying. 2024-01-14 20:32:14 -06:00			`read_verilog example.v`
			`show -pause # first`
			`proc`
			`show -pause # second`
			`opt`
			`show -pause # third`