mirror of https://github.com/YosysHQ/yosys.git
34 lines
735 B
Plaintext
34 lines
735 B
Plaintext
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read_verilog <<EOT
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module sync_sync(input clk, we, input [4:0] aw, aa, ab, input [3:0] wd, output reg [3:0] ra, rb);
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reg [3:0] mem[0:31];
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always @(posedge clk)
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if (we) mem[aw] <= wd;
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always @(posedge clk)
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ra <= mem[aa];
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always @(posedge clk)
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rb <= mem[ab];
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endmodule
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EOT
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synth_fabulous -top sync_sync
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cd sync_sync
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select -assert-count 1 t:RegFile_32x4
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design -reset
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read_verilog <<EOT
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module async_sync(input clk, we, input [4:0] aw, aa, ab, input [3:0] wd, output reg [3:0] ra, rb);
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reg [3:0] mem[0:31];
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always @(posedge clk)
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if (we) mem[aw] <= wd;
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always @(posedge clk)
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ra <= mem[aa];
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always @(*)
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rb <= mem[ab];
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endmodule
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EOT
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synth_fabulous -top async_sync
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cd async_sync
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select -assert-count 1 t:RegFile_32x4
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