mirror of https://github.com/YosysHQ/yosys.git
21 lines
335 B
Plaintext
21 lines
335 B
Plaintext
|
read_verilog -sv <<EOF
|
||
|
|
module top;
|
||
|
|
logic x;
|
||
|
|
logic z;
|
||
|
|
assign z = 1'b1;
|
||
|
|
always_comb begin
|
||
|
|
logic y;
|
||
|
|
case (x)
|
||
|
|
1'b0:
|
||
|
|
y = 1;
|
||
|
|
endcase
|
||
|
|
if (z)
|
||
|
|
x = y;
|
||
|
|
else
|
||
|
|
x = 1'b0;
|
||
|
|
end
|
||
|
|
endmodule
|
||
|
|
EOF
|
||
|
|
logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process" 1
|
||
|
|
proc
|