mirror of https://github.com/YosysHQ/yosys.git
30 lines
575 B
Verilog
30 lines
575 B
Verilog
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module pass_through_a(
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input wire [31:0] inp,
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output wire [31:0] out
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);
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assign out[31:0] = inp[31:0];
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endmodule
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module top_a(
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input wire signed [31:0] inp,
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output wire signed [31:0] out
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);
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pass_through_a pt(inp[31:0], out[31:0]);
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endmodule
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// tests both module declaration orderings
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module top_b(
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input wire signed [31:0] inp,
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output wire signed [31:0] out
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);
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pass_through_b pt(inp[31:0], out[31:0]);
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endmodule
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module pass_through_b(
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input wire [31:0] inp,
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output wire [31:0] out
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);
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assign out[31:0] = inp[31:0];
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endmodule
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