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17 lines
428 B
Systemverilog
17 lines
428 B
Systemverilog
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// Test implicit port connections
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module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
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assign cout = cin;
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assign result = a + b;
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endmodule
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module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);
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wire cin = 1;
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alu alu (
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.a(a),
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.b, // Implicit connection is equivalent to .b(b)
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.cin(), // Explicitely unconnected
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.cout(cout),
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.result(alu_result)
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);
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endmodule
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