mirror of https://github.com/YosysHQ/yosys.git
66 lines
1.5 KiB
Verilog
66 lines
1.5 KiB
Verilog
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// test_simulation_mod_1_xx.v
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module f1_test(in1, in2, out);
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input in1;
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input in2;
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output out;
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wire synth_net_0;
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wire synth_net_1;
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BUF synth_BUF_0(.in(synth_net_1), .out(out
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));
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DIV1 synth_DIV(.in1(in1), .in2(in2), .rem(synth_net_0), .out(synth_net_1
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));
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endmodule
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// test_simulation_always_31_tt.v
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module f2_test(clk, cond, data);
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input cond;
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input clk;
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output data;
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wire synth_net;
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wire synth_net_0;
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wire synth_net_1;
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wire synth_net_2;
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wire synth_net_3;
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wire synth_net_4;
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wire synth_net_5;
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wire synth_net_6;
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wire synth_net_7;
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wire synth_net_8;
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wire synth_net_9;
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wire synth_net_10;
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wire synth_net_11;
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wire tmp;
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AND2 synth_AND(.in({synth_net_0, synth_net_1}), .
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out(synth_net_2));
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AND2 synth_AND_0(.in({synth_net_3, synth_net_4}), .out(
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synth_net_5));
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AND2 synth_AND_1(.in({synth_net_6, synth_net_7}), .out(
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synth_net_8));
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AND2 synth_AND_2(.in({synth_net_9, synth_net_10}), .out(
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synth_net_11));
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BUF synth_BUF(.in(synth_net), .out(synth_net_0));
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BUF
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synth_BUF_0(.in(data), .out(synth_net_3));
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BUF synth_BUF_1(.in(synth_net_8)
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, .out(tmp));
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BUF synth_BUF_2(.in(tmp), .out(synth_net_9));
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MUX2 synth_MUX(.
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in({synth_net_2, synth_net_5}), .select(cond), .out(synth_net_6));
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MUX2
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synth_MUX_0(.in({synth_net_1, synth_net_4}), .select(cond), .out(synth_net_7
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));
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FF synth_FF(.d(synth_net_11), .clk(clk), .q(data));
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VCC synth_VCC(.out(
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synth_net));
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VCC synth_VCC_0(.out(synth_net_1));
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VCC synth_VCC_1(.out(
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synth_net_4));
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VCC synth_VCC_2(.out(synth_net_10));
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endmodule
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