mirror of https://github.com/YosysHQ/yosys.git
13 lines
143 B
Verilog
13 lines
143 B
Verilog
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module task_global();
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reg [7:0] temp_out;
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reg [7:0] temp_in;
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task convert;
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begin
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temp_out = (9/5) *( temp_in + 32);
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end
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endtask
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endmodule
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