mirror of https://github.com/YosysHQ/yosys.git
48 lines
1.6 KiB
Verilog
48 lines
1.6 KiB
Verilog
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//-----------------------------------------------------
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// This is my second Verilog Design
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// Design Name : first_counter
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// File Name : first_counter.v
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// Function : This is a 4 bit up-counter with
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// Synchronous active high reset and
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// with active high enable signal
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//-----------------------------------------------------
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module first_counter (
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clock , // Clock input of the design
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reset , // active high, synchronous Reset input
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enable , // Active high enable signal for counter
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counter_out // 4 bit vector output of the counter
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); // End of port list
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//-------------Input Ports-----------------------------
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input clock ;
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input reset ;
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input enable ;
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//-------------Output Ports----------------------------
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output [3:0] counter_out ;
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//-------------Input ports Data Type-------------------
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// By rule all the input ports should be wires
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wire clock ;
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wire reset ;
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wire enable ;
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//-------------Output Ports Data Type------------------
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// Output port can be a storage element (reg) or a wire
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reg [3:0] counter_out ;
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//------------Code Starts Here-------------------------
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// Since this counter is a positive edge trigged one,
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// We trigger the below block with respect to positive
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// edge of the clock.
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always @ (posedge clock)
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begin : COUNTER // Block Name
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// At every rising edge of clock we check if reset is active
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// If active, we load the counter output with 4'b0000
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if (reset == 1'b1) begin
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counter_out <= 4'b0000;
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end
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// If enable is active, then we increment the counter
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else if (enable == 1'b1) begin
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counter_out <= counter_out + 1;
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end
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end // End of Block COUNTER
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endmodule // End of Module counter
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